The invention relates to image sensors and, more particularly, to a complimentary metal oxide semiconductor (CMOS) image sensor able to perform analog correlated double sampling (CDS).
Generally, an image sensor is an apparatus that captures images from objects by using the property that silicon semiconductors react with visible light. Most previous image sensors have used charge coupled devices (CCD) as image capturing devices.
However, current CMOS technology has matured to the point that the imagers implemented using CMOS transistors are becoming more popular. CMOS imagers have an advantage over CCD imagers in that supplementary analog and digital circuits can be integrated together with a CMOS image sensing portion on a single chip with very low cost, which makes it possible for the CMOS image sensor to have analog-to-digital conversion circuits and other image processing logic circuits integrated on a single imager.
The on-chip analog-to-digital conversion circuits are comprised of as many comparators as columns in a pixel array of the CMOS image sensor and the picture quality of the CMOS image sensor depends largely on the quality of these comparators that convert analog pixel signals into digital signals.
FIG. 1 is a block diagram illustrating a conventional CMOS image sensor with the function of correlated double sampling. As shown in FIG. 1, the conventional CMOS image sensor includes a pixel array 100, a comparator array 200, a line buffer 300, a ramp signal generator 400, a digital controller 500 and a row decoder 600. The pixel array 100 has unit pixels arranged in the Bayer Pattern and the ramp signal generator 400 generates a ramp signal (as a reference signal for comparison) that is required to find a digital value according to an input analog signal from the pixel. The line buffer 300 consists of 4 arrays of dynamic latch circuits to store the digital value from the comparator array 200 and the digital controller 500 controls the row decoder 600, the line buffer 300 and the ramp generator 400, and performs additional image signal processing. The row decoder 600 selects a specific row of the pixel array 100 to read out the analog pixel signals under the control of the digital controller 500.
When the row decoder 600 selects a row line of the pixel array 100, the analog pixel signals are input to the comparator array 200, along with the ramp signal produced by the ramp signal generator 400. The comparators of the comparator array 200 compare the analog pixel signals with the ramp signal to find the digital pixel signals for analog-to-digital conversion.
The comparator array 200 has as many comparators as columns in the pixel array 100 and these comparators perform the analog-to-digital conversion on a row-by-row basis. The converted digital data (signals) are stored in the line buffer 300 on a column by column basis. The digital pixel signals stored in the line buffer 300 are then transferred to the digital controller 500, which performs the image processing on them and then outputs the digital image signals through the output pins of the CMOS image sensor.
FIG. 2 is a block diagram illustrating the analog-to-digital conversion circuits of a column of the conventional CMOS image sensor in FIG. 1. Additionally, FIG. 3 is a waveform of ramp signal to be compared with the analog pixel signal. There are two ramps in the overall ramp signal, which actually perform two analog-to-digital conversions for correlated double sampling (CDS).
Referring to FIG. 2, analog-to-digital conversion is carried out by a comparator 210, which is a so-called column ADC(analog-to-digital converter), to compare the analog signal obtained from a unit pixel 110 with the ramp signal from the ramp signal generator 400. The resulting output signal of the comparator 210 controls the latch 310 to catch and keep the digital gray code that becomes a digital pixel signal in gray code. The gray counter (not shown) is used for minimal error owing to the asynchronous output signal of the comparator 210.
The unit pixel 110 includes a photodiode 32 to generate a voltage from an image of an object; a transfer transistor Tx to cut the current pass, which will give the photodiode the chance to collect the photo-generated electrons to produce the pixel voltage; and a source-follower (or drive) transistor Dx driven by the photodiode voltage transferred through the transfer transistor Tx, which has a function to safely transfer the pixel voltage to the comparator. The unit pixel 110 also includes a reset transistor Rx that has two functions, to flush out all the electrons in the photodiode and to apply a reset signal to a gate of the source-follower transistor Dx; a selection transistor Sx to let the source-follower voltage out to a comparator 210; and a bias current source Is to supply the bias current to the source-follower transistor Dx.
To reduce fixed pattern noise (FPN), correlated double sampling (CDS) is used when reading the pixel data. CDS includes two phases, reading reset voltage and reading data voltage. To read the reset voltage, the transfer transistor Tx should be turned off, the reset transistor Rx is to be on for a time long enough to charge the floating node connected to the gate of source-follower transistor Dx up to VDD and then off, and the select transistor Sx must be on to apply the output voltage of the source-follower to the comparator. After the completion of AD(analog-to-digital) conversion cycle, the digital value of the pixel reset voltage is stored in the reset bank of line buffer.
To read the data voltage, the transfer transistor Tx is turned on for some time long enough to complete the process of charge sharing of the photodiode and the floating node of the Dx transistor and then off, and the select transistor Sx is turned on to apply the data voltage of the transistor Dx to the comparator for AD conversion. During the second phase, the Rx transistor is always off. After the second phase, the digital value of pixel data is stored in the data bank of line buffer. The actual CDS process is carried out by the digital control block 500, which digitally subtracts the reset value from the data value, to filter out all the signal sources of fixed pattern noise.
The process of AD conversion of this imager is simple. When the ramp generator 400, a simple switched-capacitor integrator, starts to generate a ramp signal, the digital control block 500 starts to count the gray code and the gates of digital latches in the line buffer 300 controlled by the comparator 200 that compares the ramp signal (+) and the pixel voltage (xe2x88x92), opens the gates of latches when the ramp signal is higher than the pixel voltage, and closes the gates when it is lower are open and ready for the digital latches to follow the codes of the gray counter. The comparator 200 then closes the gates of latches in the line buffer 300 when the ramp signal is the same as, or lower than, the pixel voltage, which means that the latches of the column controlled by the comparator of that column keep the digital value in gray code converted from the analog pixel voltage. In other words, the ramp generator scans from the voltage higher than the maximum possible pixel voltage to the voltage lower than the minimum possible pixel voltage so that the comparator can convert all the analog pixel voltages to digital codes. The gray codes in the line buffer are then transferred to the digital control block 500, converted to the binary codes, and processed with the CDS operation after the completion of AD conversion of a full row of pixel voltages.
FIG. 4 is a circuit diagram of the conventional comparator of FIG. 2. However, the detailed description will be omitted because this CMOS differential amplifier is well known to those skilled in the art to which the subject matter pertains.
Typically, a CMOS differential amplifier has an offset voltage and, for the case that a few hundreds of comparators are implemented with such differential amplifiers, the offset voltages of the comparators are not uniform. Therefore, these mismatches of offset voltages of comparators result in the fixed pattern noise in the image captured by this imager. That is why CDS is important in this type of AD conversion. But the traditional CDS performed in the imager of FIG. 1 is done digitally, which causes quantization noise.
FIG. 5 is a block diagram of the line buffer 300 of FIG. 1. Referring to FIG. 5, two registers of 8-bit or 9-bit latch cells are required for one pixel value owing to CDS operation.
One weak point that the comparator implemented with the CMOS differential amplifier has is that when it is not actually comparing, the static bias currents are still flowing, which results in poor power efficiency. Poor efficiency is a serious defect when applying sensors to mobile applications.
Another weak point is that it is impossible to use a specific gamma correction for the pixel analog signals because the start voltage of the ramp signal is different from one another due to the various offset voltages of the comparators.
The disclosed CMOS image sensor may include an image capturer for capturing an image for analog image signal from an object and an analog-to-digital converter that converts the analog image signal to a digital value using a ramp signal. In such an arrangement, the analog-to-digital converter may include a chopper-type comparator receiving the analog image signal and the ramp signal and a first capacitor that receives a start voltage of the ramp signal and charging a voltage level corresponding the start voltage of the ramp signal in a reset mode and for receiving a down-ramping signal of the ramp signal in a count mode in order to remove an device offset voltage. The CMOS image sensor may also include a ramp signal generator providing the ramp signal to the analog-to-digital converter.
In a rest mode, the start voltage of the ramp signal is charged in the first capacitor and a reset voltage of the image capturer is simultaneously charged in the chopper-type comparator. In a charge transfer mode, the analog image signal from the image capturer is provided to the chopper-type comparator. In a count mode, the down-ramping signal of the ramp signal is provided to the chopper-type comparator in a count mode.
The disclosed apparatus may use analog correlated double sampling, which the CDS is carried out based on analog signals, rather than on conventional digital correlated double sampling carried out after converting analog signals from a pixel to digital signals.
In the disclosed apparatus, an analog signal and an offset voltage from a pixel of the CMOS image sensor are stored in a second capacitor, the ramp signal and the offset voltage are stored in a third capacitor, and then the offset voltage is removed by a switching operation between the second and third capacitors.
Also disclosed is a a method for removing a device offset voltage in a CMOS image sensor. The method may include charging a start voltage of a ramp signal in a capacitor and simultaneously charging a rest voltage of an image capturer in a chopper-type comparator in a reset mode and providing to the chopper-type comparator an analog image signal from the image capturer in a charge transfer mode. The method may also include providing a down-ramping signal of the ramp signal to the chopper-type comparator in a count mode.